High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed

Design architectures of the CMOS power amplifier for 2.4 GHz ISM band applications: An overview

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications

Multichannel Time Synchronization Based on PTP through a High Voltage Isolation Buffer Network Interface for Thick-GEM Detectors

Data logging and complex algorithm implementations acting on multichannel systems with independent devices require the use of time synchronization. In the case of Gas Electron Multipliers (GEM) and Thick-GEM (THGEM) detectors, the biasing potential can be generated at the detector level via DC to DC converters operating at floating voltage. In this case, high voltage isolation buffers may be used to allow communication between the different channels. However, their use add non-negligible delays in the transmission channel, complicating the synchronization. Implementation of a simplified precise time protocol is presented for handling the synchronization on the Field Programmable Gate Array (FPGA) side of a Xilinx SoC Zynq ZC7Z030. The synchronization is done through a high voltage isolated bidirectional network interface built on a custom board attached to a commercial CIAA_ACC carrier. The results of the synchronization are shown through oscilloscope captures measuring the time drift over long periods of time, achieving synchronization in the order of nanoseconds

High Performance 128-Channel Acquisition System for Electrophysiological Signals

The increased popularity of investigations and exploits in the fields of neurological rehabilitation, human emotion recognition, and other relevant brain-computer interfaces demand the need for flexible electrophysiology data acquisition systems. Such systems often require to be multi-modal and multi-channel capable of acquiring and processing several different types of physiological signals simultaneously in realtime. Developments of modular and scalable electrophysiological data acquisition systems for experimental research enhance understanding and progress in the field. To contribute to such an endeavor, we present an open-source hardware project called High-Channel Count Electrophysiology or HiCCE, targeting to produce an easily-adaptable, cost-effective, and affordable electrophysiological acquisition system as an alternative solution for mostly available commercial tools and the current state of the art in the field. In this paper, we describe the design and validation of the entire chain of the HiCCE-128 electrophysiological data acquisition system. The system comprises of 128 independent channels capable of acquiring signal at 31.25 kHz, with 16 effective bits per channel with a measured noise level of about 3 μV. The reliability and feasibility of the implemented system have been confirmed through a series of tests and real-world applications. The modular design methodology based on the FPGA Mezzanine Card (FMC) standard allows the connection of the HiCCE-128 board to programmable system-on-chip carrier devices through the high-speed FMC link. The implemented architecture enables end users to add various high-response electrophysiological signal processing techniques in the field programmable gate arrays (FPGA) part of the system on chip (SoC) device on each channel in parallel according to application specification

The genetic architecture of the human cerebral cortex

The cerebral cortex underlies our complex cognitive capabilities, yet little is known about the specific genetic loci that influence human cortical structure. To identify genetic variants that affect cortical structure, we conducted a genome-wide association meta-analysis of brain magnetic resonance imaging data from 51,665 individuals. We analyzed the surface area and average thickness of the whole cortex and 34 regions with known functional specializations. We identified 199 significant loci and found significant enrichment for loci influencing total surface area within regulatory elements that are active during prenatal cortical development, supporting the radial unit hypothesis. Loci that affect regional surface area cluster near genes in Wnt signaling pathways, which influence progenitor expansion and areal identity. Variation in cortical structure is genetically correlated with cognitive function, Parkinson's disease, insomnia, depression, neuroticism, and attention deficit hyperactivity disorder

Collins and Sivers asymmetries in muonproduction of pions and kaons off transversely polarised protons

Measurements of the Collins and Sivers asymmetries for charged pions and charged and neutral kaons produced in semi-inclusive deep-inelastic scattering of high energy muons off transversely polarised protons are presented. The results were obtained using all the available COMPASS proton data, which were taken in the years 2007 and 2010. The Collins asymmetries exhibit in the valence region a non-zero signal for pions and there are hints of non-zero signal also for kaons. The Sivers asymmetries are found to be positive for positive pions and kaons and compatible with zero otherwise. © 2015

Genomic Dissection of Bipolar Disorder and Schizophrenia, Including 28 Subphenotypes

publisher: Elsevier articletitle: Genomic Dissection of Bipolar Disorder and Schizophrenia, Including 28 Subphenotypes journaltitle: Cell articlelink: https://doi.org/10.1016/j.cell.2018.05.046 content_type: article copyright: © 2018 Elsevier Inc

Remote Laboratory for E-Learning of Systems on Chip and Their Applications to Nuclear and Scientific Instrumentation

Configuring and setting up a remote access laboratory for an advanced online school on fully programmable System-on-Chip (SoC) proved to be an outstanding challenge. The school, jointly organized by the International Centre for Theoretical Physics (ICTP) and the International Atomic Energy Agency (IAEA), focused on SoC and its applications to nuclear and scientific instrumentation and was mainly addressed to physicists, computer scientists and engineers from developing countries. The use of e-learning tools, which some of them adopted and others developed, allowed the school participants to directly access both integrated development environment software and programmable SoC platforms. This facilitated the follow-up of all proposed exercises and the final project. During the four weeks of the training activity, we faced and overcame different technology and communication challenges, whose solutions we describe in detail together with dedicated tools and design methodology. We finally present a summary of the gained experience and an assessment of the results we achieved, addressed to those who foresee to organize similar initiatives using e-learning for advanced training with remote access to SoC platforms